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Mobile Multi-Output PWM Controller with Virtual Current SenseTM
POWER MANAGEMENT Description
The SC1403 is a multiple-output power supply controller designed to power battery operated systems. The SC1403 provides synchronous rectified buck converter control for two (3.3 V and 5 V) power supplies. An efficiency of 95% can be achieved for the two supplies. The SC1403 uses Semtech's proprietary Virtual Current SenseTM technology along with external error amplifier compensation to achieve enhanced stability and DC accuracy over a wide range of output filter components while maintaining fixed frequency operation. The SC1403 also provides a linear regulator for system housekeeping. The 5 V linear regulator takes its input from the battery; for efficiency, the output is switched to the 5V output when available. Control functions include: power up sequencing, soft start, power-good signaling, and frequency synchronization. Line and load regulation is to +/-1% of the output voltage. The internal oscillator can be adjusted to 200 kHz or 300 kHz or synchronized to an external clock. The MOSFET drivers provide >1A peak drive current for fast MOSFET switching. The SC1403 includes a PSAVE# input to select pulse skipping mode for high efficiency at light load, or fixed frequency mode for low noise operation.
SC1403
PRELIMINARY Features
3.3V and 5V dual synchronous outputs, resistor programmable to 2.5V Fixed frequency or PSAVE for maximum efficiency over wide load current range 5V / 50mA linear regulator TM Virtual Current Sense for enhanced stability Accurate low loss current limiting Out of phase switching reduces input capacitance requirements External compensation supports wide range of output filter components Programmable power-up sequence Power good output Output overvoltage & overcurrent protection with output undervoltage shutdown 4A typical shutdown current 6mW typical quiescent power
Applications
Notebook and subnotebook computers Automotive electronics Desktop DC-DC converters
Typical Application Circuit
SHDN#
V+ SYNC VL
4
COMP3
COMP5
5
BST3
BST5
DH3 L1 PHASE3 DL3
DH5 L2 PHASE5 DL5 PGND
CSH3 CSL3 FB3
CSH5 CSL5 FB5 SEQ
ON3
REF
ON5 RST# PSAV# GND
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SC1403
POWER MANAGEMENT Absolute Maximum Ratings
Parameter Supply Voltage, V+ to GND Boost Voltages, BST3, BST5, to GND PGND to GND BST3 to PHASE3; BST5 to PHASE5; CSL5, CSH5 to GND; CSL3, CSH3 to GND REF, SYNC, SEQ, PSAVE#, ON5, RESET#, VL, FB3, FB5, COMP3, COMP5 to GND ON3, SHDN# to GND VL, REF Short to GND REF Current VL Current Lead Temperature (Soldering) 10 seconds Storage Temperature Range Junction Temperature Range TLEAD TSTG TJ Symbol VIN Maximum -0.3 to +30 -0.3 to +36 0.3 -0.3 to +6 DC -2.0 to +7 Transient , 100nS -0.3V to +6 -0.3V to (V+ + 0.3V) Continuous +5 +50 +300 -65 to +200 +150 mA mA C C C
PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Units V V V V V V
Electrical Characteristics
Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit
Parameter MAIN SMPS CONTROLLERS Input Voltage Range 3.3V Output Voltage in Adjustable Mode 3.3V Output Voltage in Fixed Mode 5V Output Voltage in Adjustable Mode 5V Output Voltage in Fixed Mode Output Voltage Adjust Range Adjustable Mode Threshold Voltage Load Regulation Line Regulation
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Conditions
Min
Typ
Max
Units
6.0 V+ = 6.0 to 30V, CSL3 tied to FB3, 3V Load = 0A to current limit V+ = 6.0 to 30V, FB3 = 0V, 3V Load = 0A to current limit V+ = 6.0 to 30V, CSL5 tied to FB5, 5V Load = 0A to current limit V+ = 6.0 to 30V, FB5 = 0V, 5V Load = 0A to current limit Either SMPS 2.45 3.23 2.45 4.9 REF 0.5 Either SMPS, 0A to current limit Either SMPS, 6.0V < V+ <30; PSAVE# = VL
2
30.0 2.5 3.3 2.5 5.0 2.55 3.37 2.55 5.1 5.5 0.8 -0.4 0.05 1.1
V V V V V V V % %/V
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SC1403
POWER MANAGEMENT Electrical Characteristics (Cont.) PRELIMINARY
Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit
Parameter Current-Limit Threshold Negative OC limit Threshold Zero Crossing Threshold
Conditions CSH5 -CSL5, CSH3 -CSL3
Min 40
Typ 50 -50
Max 70
Units mV mV mV
CSH5 - CSL5, CSH3 - CSL; PSAVE# = 0V, not tested From enable to 95% full current limit with respect to fOSC SYNC = VL SYNC = 0V SYNC = VL SYNC = 0V Not Tested Not Tested Not Tested 240 CSH3 = CSH5 = 5.5V 220 170 92 94 300 300
5
Soft-Start Ramp Time Oscillator Frequency Maximum Duty Factor SYNC Input High Pulse SYNC Input Low Pulse Width SYNC Rise/Fall Time SYNC Input Frequency Range Current-Sense Input Leakage Current ERROR AMP Closed Loop Gain Closed Loop Bandwidth Out Resistance Offset Voltage
512 300 200 94 96 380 230
clks kHz % ns
200 350 3 10 kHz A
18 8 COMP3, COMP5 Internal FB - REF 15 25 2 35
V/V MHz k mV
INTERNAL REGULATOR AND REFERENCE VL Output Voltage VL Undervoltage Lockout Fault Threshold VL Switchover Lockout REF Output Voltage REF Load Regulation SHDN# = V+; 6V < V+ <30V; 0mA 2002 Semtech Corp.
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SC1403
POWER MANAGEMENT Electrical Characteristics (Cont.) PRELIMINARY
Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit
Parameter REF Sink Current REF Fault Lockout Voltage V+ Operating Supply Current V+ Standby Supply Current V+ Shutdown Supply Current Quiescent Power Consumption FAULT DETECTION Overvoltage Trip Threshold Overvoltage-Fault Propagation Delay Output Undervoltage Threshold Output Undervoltage Lockout Time Thermal Shutdown Threshold R E S E T# RESET# Trip Threshold RESET# Propagation Delay RESET# Delay Time INPUTS AND OUTPUTS Feedback Input Leakage Current Logic Input Low Voltage Logic Input High Voltage
Conditions
Min
Typ 10
Max
Units A
Falling edge VL switched over to VOUT5, both SMPS on, ILoad3 = 0A, ILoad5 = 0A V+ = 6V to 30V, SMPS off, includes current into SHDN# V+ = 6V to 30V, SHDN# = 0V SMPS enabled, FB3 = FB5 = 0V, No Load on SMPS
1.8 10 180 4 6.0
2.2 50
V A
10 mW
With respect to unloaded output voltage Output driven 2% above overvoltage trip VTH With respect to unloaded output voltage From each SMPS enabled, with respect to f OSC Typical hysteresis = +10C
7
10 1.5
15
% s
65 5000
75 6144 150
85 7000
% clks C
With respect to unloaded output voltage, falling edge; typical hysteresis = 1% Falling edge, output driven 2% below RESET# trip threshold With respect to fOSC
-13
-10 1.5
-7
% s
27,000
32,000
37,000
clks
FB3, FB5 = 2.6V ON3, PSAVE#, ON5, SHDN#, SYNC (SEQ = 0V or VL) ON3, PSAVE#, ON5, SHDN#, SYNC (SEQ = 0V or VL) 2.4
+1 0.6
A V V
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SC1403
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter Input Leakage Current Logic Output Low Voltage Logic Output High Current ON5 Pull-Down Resistance Gate Driver Sink/Source Current Gate Driver On-Resistance Non-Overlap Threshold Non-Overlap Delay Conditions ON3, PSAVE#, ON5, SHDN#, SYNC (SEQ = 0V or VL) RESET#, ISINK = 4mA RESET# = 3.5V ON5, ON3 = 0V, SEQ = REF DL3, DH3, DL5, DH5, forced to 2.5V High or low PHASE3, PHASE5, DL3, or DL5 Falling edge of DH to rising edge of DL Falling edge of DL to rising edge of DH (1V threshold on DH and DL, no capacitance on DL or DH) 10 35 1 100 1 1.5 1.0 17 75 25 115 7 Min Typ
PRELIMINARY
Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit
Max +1 0.4
Units A V mA A V nsec nsec
Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions required.
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SC1403
POWER MANAGEMENT Pin Configuration
TOP VIEW
CSH3 CSL3 FB3 COMP3 COMP5 SYNC ON5 GND REF PSAVE# RESET# FB5 CSL5 CSH5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ON3 DH3 PHASE3 BST3 DL3 SHDN# V+ VL PGND DL5 BST5 PHASE5 DH5 SEQ
PRELIMINARY Ordering Information
Device SC1403ITSTR P ackag e TSSOP-28 Temp. (TA) -40 - +85C
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices.
(28 Pin TSSOP)
Block Diagram
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SC1403
POWER MANAGEMENT Pin Descriptions
Pin # 1 2 3 Pin Name CSH3 C S L3 FB 3 Pin Function Current limit sense input for 3.3 V SMPS. Connect to the inductor side of a current sense resistor . Output voltage sense input for 3.3 V SMPS. Connect to the output side of a current sense resistor . Feedback Input for the 3.3 V SMPS; regulates at FB3 = REF (approx. 2.5 V) in adjustable mode. FB3 selects the 3.3 V fixed output voltage setting when tied to GND. Connect FB3 to a resistor divider for adjustable output mode. The output of the error amplifier for 3.3V SMPS. The output of the error amplifier for 5.0V SMPS. Oscillator Synchronization and Frequency Select. Tie to VL for 300 kHz operation; tie to GND for 200 kHz. Driven externally to SYNC between 240 kHz and 350 kHz. 5V ON/OFF Control Input. Low noise Analog Ground and Feedback reference point. 2.5 V Reference Voltage Output. Bypass to GND with 1 F minimum. Logic Control Input that disables PSAVE Mode when high. Connect to GND for normal use. Active Low Timed Reset Output. RESET# swings GND to VL. Goes high after a fixed 32,000 clock cycle delay following power up. Feedback Input for 5 V SMPS; regulates at FB5 = REF (approx. 2.5 V) in adjustable mode. FB5 selects the 5 V fixed output voltage setting when tied to GND. Connect FB5 to a resistor divider for adjustable output mode. Output voltage sense input for 5 V SMPS. Connect to the output side of a current sense resistor . Current limit sense input for 5 V SMPS. Connect to the inductor side of a current sense resistor . Input that selects SMPS sequence for RESET#. Gate Drive Output for the 5 V, high side N-Channel switch. Switching Node (inductor) connection. Boost capacitor connection for high side gate drive.
PRELIMINARY
4 5 6 7 8 9 10 11 12
COMP3 COMP5 SYNC ON5 GND REF PSAVE# RESET# FB 5
13 14 15 16 17 18
C S L5 CSH5 SEQ DH5 PHASE5 BST5
Note: All logic level inputs and outputs are open collector TTL compatible.
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SC1403
POWER MANAGEMENT Pin Descriptions (Cont.)
Pin # 19 20 21 22 23 24 25 26 27 28 Pin Name D L5 PGND VL V+ SHDN# D L3 BST3 PHASE3 DH3 ON3 Pin Function Gate Drive Output for the low side synchronous rectifier MOSFET. Power Ground. 5 V Internal Linear Regulator Output. Battery Voltage Input. Shutdown Control Input, active low. Gate Drive Output for the low side synchronous rectifier MOSFET. Boost Capacitor Connection for high side gate drive. Switching Node (inductor) Connection. Gate Drive Output for the 3.3 V, high side N-Channel switch. ON/OFF Control Input.
PRELIMINARY
Note: All logic level inputs and outputs are open collector TTL compatible.
Block Diagram
V+ V+ SYNC PSAVE
VL 5V REG
VL
VL VIN
BST3 VIN DH3 LX3 +3.3V DL3 VL LS CSL5
EN DELAY HS
BST5
DH5 LX5 VL +5V
OSC
LS
DL5
PGND 50mV OC 3V CTL LOGIC 5V CTL LOGIC OC 50mV
7.5m V
PS
PS
7.5m V
2.5m V
POL
POL
2.5m V
CSH3 CSL3
PWM MODULATOR
OV FAULT
PWM MODULATOR
CSH5 CSL5
+10%
-25% COMP3 COMP5
UV FAULT
0.6 FB3 0.6V REF 2.5V REF DELAY V+ CSL3 CSL5 CURRENT RAMP TIMER BV SS 3 TIME/ON5 VL 2 0.5 POW ER-ON SEQUENCE LOGIC 2.0 RESET FB5
SEQ
RUN/ON3
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SC1403
POWER MANAGEMENT Functional Information
Detailed Description The SC1403 is a versatile multiple-output power supply controller designed to power battery operated systems. Out of phase switching design is adopted to improve signal quality and reduce input RMS current, therefore reducing size of input filter inductor and capacitors. The SC1403 provides synchronous rectified buck control in fixed frequency forced-continuous mode and hysteretic PSAVE mode for two switching power supplies over a wide load range. The two switchers have on-chip preset output voltage of 5.0V and 3.3V. An external resistor divider can be used to set the switcher outputs from 2.5V to 5.5V. The control and fault monitoring circuitry associated with each PWM controller includes digital softstart, turn-on sequencing, voltage error amplifier with built-in slope compensation, pulse width modulator, power save, over-current, over-voltage and under-voltage fault protection. One linear regulator and a precision reference voltage are also provided by the SC1403. The 5V/50mA linear regulator takes input from the battery to power the gate drivers, however to improve efficiency, the 5V switcher output is used instead when available. Semtech's proprietary Virtual Current SenseTM provides greater advantages in the aspect of stability and signal to noise ratio than the conventional current sense method. PWM control There are two separate PWM control blocks for the 3V and 5V switchers. They are out-of-phase with each other. The interleaved topology offers greater advantage over in-phase solutions. It reduces steady state input filter requirements by reducing current drawn from the filter capacitors. To avoid both switchers switching at the same instance, there is a built-in delay between the on-time of the 3.3V switcher and 5V switcher, the amount of which depends on the input voltage (see Out-of-Phase Switching). The PWM provides two modes of control over the entire load range. The SC1403 operates in forced continuous conduction mode as a fixed frequency peak current mode controller with falling edge modulation. Current sense is done differently than that in the conventional peak current mode control. Semtech's proprietary Virtual Current SenseTM emulates the necessary inductor current information for proper functioning of the IC. In order to accommodate a wide range of output filters, a COMP pin is also available for compensating the error amplifier externally. A nominal gain of 18 is used in the error amplifier to further improve the system loop gain response and the output transient behavior. When the switcher is operating in continuous conduction mode, the highside MOSFET is turned on at the beginning of each switching cycle. It is turned off when the desired duty cycle is reached. Active shootthrough protection delays the turn-on of the lower MOSFET until the phase node drops below 2.5V. The low-side MOSFET remains on until the beginning of the next switching cycle. Again, active shoot-through protection ensures
PRELIMINARY
that the gate to the low-side MOSFET has dropped low before the high-side MOSFET is turned on. Under light load conditions when the PSAVE pin is low, the SC1403 operates as a hysteretic controller in the discontinuous conduction mode to reduce its switching frequency and switching bias current. The switching of the output MOSFET does not depend on a given oscillator frequency, but on the hysteretic FB trip voltage set around the reference. When entering PSAVE mode, if the minimum (valley) inductor current measured across the CSH and CSL pins is below the PSAVE threshold for four switching cycles, the virtual current sensing circuitry is shutdown and PWM switches from forced continuous to hysteretic mode. If the minimum (valley) inductor current is above the threshold for four switching cycles, PWM control changes from hysteretic to forced continuous mode. The SC1403 provides built-in hysteresis to prevent chattering between the two modes of operation. Gate Drive / Control The gate drivers on the SC1403 are designed to switch large MOSFETs up to 350KHz. The high-side gate driver is required to drive the gates of high-side MOSFET above the V+ input. The supply for the gate drivers is generated by charging a boostrap capacitor from the VL supply when the low-side driver is on. Monitoring circuitry ensures that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. In continuous conduction mode, the low-side driver output that controls the synchronous rectifier in the power stage is on when the high-side driver is off. Under light load conditions when PSAVE pin is low, the inductor ripple current will approach the point where it reverses polarity. This is detected by the low-side driver control and the synchronous rectifier is turned off before the current reverses, preventing energy drain from the output. The low-side driver operation is also affected by various fault conditions as described in the Fault Protection section. Internal Bias Supply The VL linear regulator provides a 5V output that is used to power the gate drivers, 2.5V reference and internal control section of the SC1403. The regulator is capable of supplying up to 50mA (including MOSFET gate charge current). The VL pin should be bypassed to GND with 4.7uF to supply the peak current requirements of the gate driver outputs. The regulator receives its input power from the V+ battery input. Efficiency is improved by providing a boot-strapping mode for the VL bias. When the 5V SMPS output voltage reaches 5V, internal circuitry detects this condition and turns on a PMOS pass device between CSL5 and VL. The internal VL regulator is then disabled and the VL bias is provided by the high efficiency switcher. The REF output is accurate to +/- 2% over temperature. It is capable of delivering 5mA max and should be bypassed with 1uF minimum capacitor. Loading the REF pin will reduce the REF voltage slightly.
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SC1403
POWER MANAGEMENT Functional Information
Loading Resistance (ohm) Deviation from Vref = 2.4920V 511 2.67K 49.9K 255K 1Meg
PRELIMINARY
SH D N Low ON3 X Low ON5 X Low MODE Shutdown Standby DESCRIPTION Minimum bias current VREF and VL regulator enable Both SMPS Running
8.3mV 3.1mV 0.5mV
0.3mV
0mV
High
Current Sense (CSH, CSL) The output current of the power supply is sensed as the voltage drop across an external resistor between CSH and CSL pins. Overcurrent is detected when the current sense voltage exceeds +/50mV. A positive over-current will turn off the high-side driver; a negative over-current will turn off the low-side driver, each on a cycle by cycle basis. Oscillator When the SYNC pin is set high the oscillator runs at 300KHz; when SYNC is set low the frequency is 200KHz. The oscillator can also be synchronized to the falling edge of a clock on the SYNC pin with a frequency between 240KHz and 350KHz. In general, 200KHz operation is used for highest efficiency, and the 300KHz for minimum output ripple and/or smaller filter components. Fault Protection In addition to cycle-by-cycle current limit, the SC1403 monitors over-temperature, and output over-voltage and under-voltage conditions. The over-temperature detect will shut the part down if the die temperature exceeds 150C with 10C of hysteresis. If either SMPS output is more than 10% above its nominal value, both SMPS are latched off and synchronous rectifiers are latched on. To prevent the output from ringing below ground in a fault condition, a 1A Schottky diode should be placed across each output. Two different levels of undervoltage are detected. If the output falls 10% below its nominal output, the RESET output is pulled low.If the output falls 25% below its nominal output following a start-up delay, both SMPS are latched off. Both of the latched fault modes persist until SHDN or RUN/ON3 is toggled or the V+ input is brought below 1V. Shutdown and Operating Modes Holding the SHDN pin low disables the SC1403, reducing the V+ input current to less than 10uA. When SHDN goes high, the part enters a standby mode where the VL regulator and VREF are enabled. Turning on either SMPS will put the SC1403 in run mode.
High
High
High
Run Mode
Output Voltage Selection If FB is connected to ground, internal resistors setup 3.3V and 5V output voltages. If external resistors are used, the internal feedback is disabled and the output is regulated based on 2.5V reference at the FB pin. (see comment in the application design section). Power up Controls and Soft Start The user has control of the SC1403 RESET# by setting the SEQ, ON3 and ON5 pins as described in the following table. Each SMPS contains its own counter and DAC to gradually increase the current limit at startup to prevent surge currents. The current limit is increased from 0, 20%, 40%, 60%, 80%, to 100% linearly over the course of 512 switching cycles. A RESET# output is also generated at startup. The RESET# pin is held low for 32K switching cycles. Another timer is used to enable the undervoltage protection. The undervoltage protection circuitry is enabled after 6144 switching cycles at which time the SMPS should be in regulation. When SEQ is set to REF, the RESET# pin only monitors the 3.3V SMPS in regulation and the 5V SMPS is ignored.
Applications Information
Reference Circuit Design Introduction The SC1403 is a versatile dual switching regulator adjustable from 2.5V to 5.5V with fixed 5V and 3.3V modes. In addition, there is an on-chip 5V linear regulator capable of supplying 50mA output current. The SC1403 is designed for notebook applications but has applications where high efficiency, small package and low cost are required.
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SC1403
POWER MANAGEMENT Functional Information (Cont.) SC1403 Startup Sequence Chart
SEQ REF REF REF REF GND GND VL VL ON3 LOW LOW HIGH HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH X HIGH/LOW X HIGH/LOW ON5 R ESET Follows 3.3V SMPS. Low. Follows 3.3V SMPS. Follows 3.3V SMPS. Low. High after both outputs are in regulation. Low. High after both outputs are in regulation.
PRELIMINARY
DESCRIPTION Independant start control mode. Both SMPSs off. 5V SMPS ON, 3.3V SMPS OFF. 3.3V SMPS ON, 5V SMPS OFF. Both SMPSs on. Both SMPSs off. 5V starts when ON3 goes high. If ON5 = HIGH, 3V is on. If ON3 = LOW, 3V is off. Both SMPSs off. 3V starts when ON3 goes high. If ON5 = HIGH, 5V is on. If ON3 = LOW, 5V is off.
Applications Information
Design Guidelines The schematic for the reference circuit is shown on page 24. The reference circuit is configured as follows: Switching Regulator 1 Switching Regulator 2 Linear Regulator Designing the Output Filter Before calculating the output filter inductance and output capacitance, an acceptable amount of output ripple current is to be determined. The maximum allowable ripple current depends on the transient requirement of the power supply. Under normal situation, the ripple current is usually set at 10 to 20% of the maximum load. However, in order to speed up the output transient response, ripple current can be much higher. In this design, we are going to set the ripple current to be 40% of maximum load. So once the ripple voltage specification is determined, the capacitor ESR is chosen. The output ripple voltage is usually specified at +/ - 1% of the output voltage. Vout1 = 3.3V @ 6A Vout2 = 5.0V @ 6A Vout3 = 5.0V @ 50mA For the reference circuit 3.3V switcher, we selected a maximum ripple voltage of 33mV. Choosing one 180uF, 4V Panasonic SP Polymer Aluminum Electrolytic Cap, of which ESR is 15 m , sets the maximum ripple current as follows:
IO = VO _ MAX ESR IO = 0.033 V = 2.2A 0.015
Checking to see if the maximum RMS current can be met by the SP cap.
I1 = - IRMS =
IO 2 I1 2 + I1 I2 + I2 2 3
I2 = +
IO 2
Irms=0.635 A << Irms_rated=3.0A The output inductance can now be found by:
LO =
(VIN _ NOM - VO) DNOM TS IO
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SC1403
POWER MANAGEMENT Applications Information
where Vin_nom=15V, Vo=3.3V, D=Vo/Vin_nom, Fs=300KHz, Ts=3.33uS and Io=2.2 A. Lo is subsequently calculated to be 3.9uH. For the interest of this design, Lo is chosen to be 4.7uH. Choosing Current Sense Resistor Since the SC1403 implements Virtual Current SenseTM, the external current sense resistor is not required for the control loop. However, it is required for cycle-by-cycle current limit. Cycle-by-cycle current limit is enabled when the voltage across the current sense resistor exceeds 50mV nominal. Depending on the system requirement, this current limit can vary, it is usually 10 to 30% higher than the maximum load. Taking into consideration of the +/-20% variation on the 50mV, the value of the current sense resistor can be calculated using the following equation: 40mV (min) RSENSE = IPK _ OC For a DC OC trip point between 6.3A to 9.8A, Rsense is chosen to be 5.5m . Considering the maximum power dissipation, two Vishay WSL2010 11m 1% resistors are used. Choosing the Main Switching MOSFET Before choosing the main switch MOSFET, we need to know two critical parameters: voltage and current rating. In order to minimize the conduction loss, we recommend using the lowest Rds(on) for the same voltage and current rating. The maximum drain to source voltage of the switch MOSFET is mainly decided by the topology of the switcher. Since this is a buck topology,
VDS _ MAX = VIN _ MAX = 21 V
PRELIMINARY
Vendor P/N VDS (V) ID (A) Rds(0n) @ 4.5V (ohm) 0.0135 0.011 0.036 0.0085 P ackag e
S i 4886D Y IRF7413 F D S 9412 STS12NF30L
30 30 30 30
13 13 7.9 12
SO-8 SO-8 SO-8 SO-8
The following calculations are done to verify that the power dissipation of the main switch MOSFET is well within 1.86W, which is the maximum allowable power dissipation for the package.
PTOTAL _ DISS = PCONDUCTION + PSWITCHING + PGATE PCONDUCTION = Rds ( on) IRMS 2 Dnom
where Rds(on) = 0.01 @Tj=25 C and Vgs = 4.5V. In order to find Rds(on)@ Tj=100 C , use 1.40*Rds(on)@25 C . Therefore, Rds(on) @ Tj = 100 C is equal to 0.014 .
I RMS =
where
(
I1 2 + I1 I2 + I2 2 ) 3
I1 = IMAX +
Dnom =
IO _ MAX IO _ MAX = 7.1A, I2 = IMAX - = 4.9A and 2 2 VOUT
VIN _ NOM
Applying a derating of 70%, a 30V MOSFET is used in the design. The peak current of the MOSFET is determined by
IPEAK =
60mV = 11 A 5.5m
The worst case conduction loss is calculated to be 112mW. And the switching loss of the MOSFET is given by,
PSWITCHING = CRSS VIN 2 fS IOUT IG
According to the calculated voltage and current rating, Si4886DY, IRF7413, FDS9412 or STS12NF30L meets the requirement. The specs for these MOSFETs are listed in the table below. For the purpose of this exercise, STS12NF30L is chosen. Next step is to determine its power handling capability. Based on 85 C ambient temperature, 150 C junction temperature and 50 C /W thermal resistance, its power handling is calculated as follows: TJ = 150C; TA = 85C; JA= 50C/W
where Crss is the reverse transfer capacitance of the MOSFET; it is equal to 200pF for STS12NF30L, Ig is the gate driver current; it is equal to 1A for SC1403. And Vin_nom = 15V, fs = 300KHz. The switching loss is calculated to 81mW. And the gate loss is given by,
PGATE =
1 CG V 2 fS 2
where Cg=11nF, V=5V and fs=300KHz. The gate loss is calculated to be 41mW. So the total power dissipation is calculated to be 234mW and is well within the maximum power dissipation allowance of the MOSFET. No special heating sinking is required when laying out the MOSFET.
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PT =
TJ - TA 150 - 85 = = 1.30W JA 50
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SC1403
POWER MANAGEMENT Applications Information Applications Information (Cont.)
Designing the Loop There are two aspects concerning the loop design. One is the power train design and the other is the external compensation design. A good loop design is a combination of the two. In the SC1403, the control-to-output/power train response is dominated by the load impedance, the effective current sense resistor, output capacitance, and the ESR of the output caps. The low frequency gain is dominated by the output load impedance and the effective current sense resistor. Inherent to Virtual Current SenseTM, there is one additional low frequency pole sitting between 100Hz and 1KHz and a zero between 15KHz and 25KHz. To compensate for the SC1403 is easy since the output of error amplifier COMP pin is available for external compensation. A traditional pole-zeropole compensation is not necessary in the design using SC1403. To ensure high phase margin at crossover frequency while minimizing the component count, a simple high frequency pole is usually sufficient. In the reference design below, single-pole compensation method is demonstrated. And the loop measurement results are compared to that obtained from the simulation model. Transient response is also done to validate the model. Also, to help speeding up the design process, a list of recommended output caps vs. compensation caps value is given in table I. Single-Pole compensation Method Given parameters: Vin = 19V, Vout = 3.3V @ 2.2A, Output impedance, Ro = 3.3V/2.2A = 1.5 , Panasonic SP cap, Co = 180uF, Resr = 15 m , Output inductor, Lo = 4.7uH Switching frequency, Fs = 300KHz Simulated Control-to-Output gain & phase response (up to 100KHz) is plotted below
Phase (deg)
PRELIMINARY
200 150 100 50 Phase (deg) 0 -50 -100 -150 -200 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
Measured Control-to-Output gain & phase response (up to 100KHz) is plotted below.
50 40 30 20 10 Gain (dB) 0 -10 -20 -30 -40 -50 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
200 150 100 50 0 -50 -100 -150 -200 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
.
50 40 30 20 Gain (dB) 10 0 -10 -20 -30 -40 -50 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
Single-pole compensation of the error amplifier is achieved by connecting a 100pF capacitor from the COMP pin of the SC1403 to ground. The simulated feedback gain & phase response (up to 100KHz) is plotted below.
.
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SC1403
POWER MANAGEMENT Applications Information (Cont.)
25 20 15 10 Gain (dB) 5 0 -5 -10 -15 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05 Phase (deg)
PRELIMINARY
20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 1.00E+02 1.00E+03 Frequency (Hz) 1.00E+04 1.00E+05
0 -10 -20 -30 Phase (deg) -40
Simulated overall gain & phase responses (up to 100KHz) is plotted below.
80 60 40
-50
Gain (dB)
-60 -70 -80 -90 -100 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
20 0 -20 -40 -60 -80 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
Measured feedback gain & phase responses (up to 100KHz) is plotted below.
25 20 140 15 10 Gain (dB) 5 0 -5 -10 -15 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05 120 Phase (deg) 100 80 60 40 20 0 -20 1.00E+02 1.00E+03 180 160
1.00E+04 f (Hz)
1.00E+05
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SC1403
POWER MANAGEMENT Applications Information (Cont.)
Measured overall gain & phase response of the single-pole compensation using SC1403 is plotter below.
60
PRELIMINARY
Table I. is useful only if the following ESR condition is satisfied.
fO =
1 2 RESR C O
25
fo > 50KHz where Resr is the equivalent ESR of the total output caps.
Gain (dB)
-10
Transient responses of the switcher using single-pole compensation are shown below. The load steps from 0A to 3A and 3A to 6A. The applied di/dt is 2.5A/usec
-45
-80 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
180 160 140 120 Phase (deg) 100 80 60 40 20 0 -20 1.00E+02
1.00E+03 f (Hz)
1.00E+04
1.00E+05
Table I. Recommended compensation cap for different output capacitance.
Output C ap < = 180F > 180F & <1000F >1000F Recommended C ompensati on C ap Value 100pF 200pF 330pF
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SC1403
POWER MANAGEMENT Typical Characteristics
Condtions: (PSAVE enabled) Vin = 10V, ILoad= 0A to 3A Vout = 3.3V Condtions: (PSAVE disabled) Vin = 10V, ILoad= 0A to 3A Vout = 3.3V
PRELIMINARY
Condtions: Vin = 10V, ILoad= 3A to 6A Vout = 3.3V
Condtions: (PSAVE enabled) Vin = 19V, ILoad= 0A to 3A Vout = 3.3V
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SC1403
POWER MANAGEMENT Typical Characteristics (Cont.)
Condtions: (PSAVE disabled) Vin = 19V, ILoad= 0A to 3A Vout = 3.3V Condtions: (PSAVE enabled) Vin = 10V, ILoad= 0A to 3A Vout = 5.0V
PRELIMINARY
Condtions: Vin = 19V, ILoad= 3A to 6A Vout = 3.3V
Condtions: (PSAVE disabled) Vin = 10V, ILoad= 0A to 3A Vout = 5.0V
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SC1403
POWER MANAGEMENT Typical Characteristics (Cont.)
Condtions: Vin = 10V, ILoad= 3A to 6A Vout = 5.0V
PRELIMINARY
Condtions: (PSAVE disabled) Vin = 19V, ILoad= 0A to 3A Vout = 5.0V
Condtions: (PSAVE enabled) Vin = 19V, ILoad= 0A to 3A Vout = 5.0V
Condtions: Vin = 19V, ILoad= 3A to 6A Vout = 5.0V
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SC1403
POWER MANAGEMENT Applications Information
Input Capacitor Selection Input bulk capacitor is selected based on the input RMS current requirement of the converter. The input RMS ripple current can be calculated as follows: External Feedback Design In order to optimize the ripple voltage during Power Save mode, it is strongly recommended to use external voltage dividers (R10 and R9 for 5V power train; R8 and R11 for 3.3V power train) to achieve the required output voltages. In addition, a 56pF (C22 for 5V and C21 for 3.3V) cap is recommended connecting from the output to both feedback pins (pin # 3 and #12). The signal to noise ratio is therefore increased due to the added zeroes. Input Capacitor Selection/Out-of-phase Switching The SC1403 uses out-of-phase switching between the two converters to reduce input ripple current, enabling the use of smaller, cheaper input capacitors when compared to in-phase switching. The two approaches are shown in the following figures. The first figure shows in-phase switching: I3in is the input current drawn by the 3.3V converter, I5in is the input current drawn by the 5V converter. The two converters start each switching cycle simultaneously, resulting in a significant amount of overlap. This overlap increases the peak current. The total input current to the converter is the third trace Iin, which shows how the two currents add together. The fourth trace shows the current flowing in and out of the input capacitors. In-phase Switching
Ii 3n
PRELIMINARY
IRMS = VOUT (VIN - VOUT )
Iout VIN
The worst case input RMS current occurs at 50% duty cycle and therefore under this condition the Irms current can be approximated by
IRMS =
ILOAD 2
Therefore, for a maximum load current of 6A, the input capacitor should be able to handle 3A of ripple current. For the reference circuit design, there are two such regulators that operate out-ofphase. Therefore, 3A ripple current is the most these two converters will see under the normal steady state operating condition. For the combined two regulators, one SMT OS-CON 47uF, 25V is used. The maximum allowable ripple current for the cap is rated 3.5A rms @ 100KHz, 45 C . Considering the derating at higher ambient temperature and higher operating frequency, two additional MLC caps are also used (Vishay MLC, 12uF, 25V, Y5V, size 2225). Choosing Synchronous MOSFET and Schottky diode Since this is a buck topology, the voltage and current ratings of the synchronous MOSFET is the same as the main switching MOSFET. It makes sense cost-volume-wise to use the same MOSFET for the main switch as for the synchronous MOSFET. Therefore, STS12NF30L is used again in the design for synchronous MOSFET. To improve overall efficiency, an external schottky diode is used in parallel to the synchronous MOSFET. The freewheeling current is going into the schottky diode instead of the body diode of the synchronous MOSFET, which usually has very high forward drop and slow transient behavior. It is really important when laying out the board, to place both the synchronous MOSFET and Schottky diode close to each other to reduce the current ramp-up and rampdown time due to parasitic inductance between the channel of the MOSFET and the Schottky diode. The current rating of the Schottky diode can be determined by the following equation, 100n = 0.2A IF _ AVG = ILOAD TS where 100nsec is the estimated time between the MOSFET turning off and the Schottky diode taking over and Ts = 3.33uS. Therefore a Schottky diode with a forward current of 0.5A is sufficient for this design.
I5 i n
Ii n
a ve ra g e 0
0 Icap
The next figure shows out-of-phase switching. Since the 3.3V and 5V converters are spaced apart, there is no resulting overlap. This results in a two benefits; the peak current is reduced and the frequency content is higher, both of which make filtering easier. The third trace shows the total input current, and the fourth trace shows the current in and out of the input capacitors. The RMS value of this current is significantly lower than the in-phase case and allows for smaller capacitors due to reduced RMS current ratings.
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SC1403
POWER MANAGEMENT
Out-of-phase Switching
PRELIMINARY
Vin > 9.6V: 3.3V turn-on leads 5V turn-on by 41% of the switching period. With Vin > 9.6V it is always possible to achieve no overlap, which minimizes the input ripple current. At Vin = 9.6V there is no overlap, but the 3.3V turn-on is nearing the 5V turn-off converter. 6.7 < Vin < 9.6V: 3.3V turn-on leads 5V turn-on by 59% of the period. To prevent the 3V turn-on from coinciding with the 5V turnoff (which could affect either output), the 5V pulse is delayed in time slightly such that the 3V turn-on occurs before the 5V turn-off. This creates a small overlap between the 3V turn-on and the 5V turn-off, with a resulting slight increase in RMS input ripple, but this is preferred since it greatly reduces noise problems caused by simultaneous transitions. Note that at Vin = 6.7, the 3V turn-off is nearing the 5V turn-on. Vin < 6.7 volts: 3.3V turn-on leads 5V turn-on by 64% of the period. The 5V turn-on is delayed slightly more to add separation between the 3V turn-off and 5V turn-on. This leads to more overlap, but at this point overlap is unavoidable. Input ripple current calculations: The following equations provide quick approximations for input ripple current: D3 = 3.3V duty cycle = 3.3/Vin D5 = 5V duty cycle = 5/Vin I3 = 3.3V load current I5 = 5V load current Dovl = overlapping duty cycle of the 3V and 5V pulses, which varies according to input voltage: Vin > 9.6V: Dovl = 0 9.6V > Vin > 6.7V: Dovl = D5 - 0.41 6.7V > Vin Dovl = D5 - 0.36 Iin = D3 . I3 + D5 . I5 (average current drawn from Vin)
0 Ip ca
Ii 3n
Ii 5n
a ve ra g e In i 0
0 Ip ca
As the input voltage is reduced, the duty cycle of both converters increases. For inputs less than 8.3 volts it is impossible to prevent overlap when producing 3.3V and 5V outputs, regardless of the phase relationship between the converters. This can be seen in the following figure.
p e ri d o p h a se l a d e
Ii 3n
Ii 5n In i
a ve ra g e
0
(Isw_rms)2 = Dovl . (I3 + I5)2 + (D3 - Dovl) . I32 + (D5 -Dovl) . I52 Isw_rms = rms current flowing into 3V and 5V SMPS Irms_cap =
Isw_rms + Iin
2 2
From an input filter standpoint it is desirable to make the minimize the overlap, but it is also desirable to keep the turn-on and turn-off transitions of the two converters separated in time, otherwise the two converters may affect each other due to switching noise. The SC1403 implements this by changing the phase relationship between the converter depending on the input voltage.
Inp ut voltage Vin > 9.6 V 9.6V > Vin > 6.7V 6.7 > Vin
2002 Semtech Corp.
Phase lead from 3V conver ter rising edge to 5V conver ter rising edge 41% of switching p eriod 59% of switching p eriod 64% of switching p eriod
20
The worst-case ripple current varies by application. For the case of I3 = I5 = 6A, the worst-case ripple occurs at Vin = 7.5V, at which point the rms capacitor ripple current is 4.2 amps. To handle this the reference design uses 4 paralleled ceramic capacitors, (Murata GRM32NF51E106Z, 10 uF 25V, size 1210). Each capacitor is rated at 2.2 Amps, allowing for derating at higher temperatures.
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SC1403
POWER MANAGEMENT
Operation below 6V input The SC1403 will operate below 6V input voltage with careful design, but there are limitations. The first limitation is the maximum available duty cycle from the SC1403, which limits the obtainable output voltage. The design should minimize all circuit losses through the system in order to deliver maximum power to the output. A second limitation with operation below 6V is transient response. When load current increases rapidly, the output voltage drops slightly; the feedback loop normally increases duty cycle briefly to bring the output voltage back up. If duty cycle is already near the maximum limit, the duty cycle cannot increase enough to meet the demand, and the output voltage sags more than normal. This problem can not be solved by changing the feedback compensation, it is a function of the input voltage, duty cycle, and inductor and capacitor values. If an application requires 5V output from an input voltage below 6V, the following guidelines should be used: 1 - Set the switching frequency to 200 kHz (Tie SYNC to GND). This increases the maximum duty cycle compared to 300 kHz operation. 2 - Minimize the resistance in the power train. Select MOSFETs, inductor, and current sense resistor to provide the lowest resistance as is practical. 3 - Minimize the pcb resistance for all traces carrying high current. This includes traces to the input capacitors, MOSFETS and diodes, inductor, current sense resistor, and output capacitor. 4 - Minimize the resistance between the SC1403 circuit and the power source (battery, battery charger, AC adaptor). 5 - Use low ESR capacitors on the input to prevent the input voltage dropping during on-time. 6 - If large load transients are expected, high capacitance and low ESR capacitors should be used on both the input and output. Overvoltage Test Measuring the overvoltage trip point can be problematic. Any buck converter with synchronous MOSFETS can act as a boost converter, sending energy from output to input. In some cases the energy sent to the input is enough to drive the input voltage beyond normal levels, causing input overvoltage. To prevent this, enable the SC1403 PSAVE# feature, which effectively disables the low side MOSFET drive so that little energy, if any, is transferred back to the input. Semtech recommends the following circuit for measuring the overvoltage trip point. D1 prevents the output voltage from damaging lab supply 1. R1 limits the amount of energy that can be cycled from the output to the input. R2 absorbs the energy that might flow from output to input, and D2 protects lab supply from possible damage. The ON5 signal is monitored to indicate when overvoltage occurs. Initial conditions: Both lab supplies set to zero volts No load connected to 3V or 5V PSAVE# enabled (PSAVE# tied to GND) ON5, ON3 both enabled DVMs monitoring ON5 and the output under test. Oscilloscope probe connected to Phase Node of the output under test (not strictly required). Set lab supply 2 to provide 10V at the SC1403 input. The phase node of the output being tested should show some switching activity. The ON5 pin should be above 4V. Slowly increase lab supply 1 until the output under test rises slightly above it's normal DC level. As the input lab supply 1 increases, switching activity at the phase node will cease. The ON5 pin should remain above 4V. Increase lab supply 1 in very small increments, monitoring both ON5 and the output under test. The overvoltage trip point is the highest voltage seen at the output before ON5 pulls low (approximately 0.3V). Do not record the voltage seen at the output after ON5 has pulled low; when ON5 pulls low, the current flowing in D1 changes, corrupting the voltage seen at the output.
to DVM D1 e.g. 1N4004 R1 75 1/2W 1K Lab Supply 1
PRELIMINARY
D1 e.g. 1N4004
Vin
Output under test VL
Lab Supply 2
R2 470 1/2W
SC1403 Evaluation Board
ON5
to DVM
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SC1403
POWER MANAGEMENT Typical Characteristics
5V Line Regulation
5.03 5.025 5.02 5V@0A 5.015 Vout (V) 5.01 5.005 5 4.995 4.99 10 12 14 16 Vin (V) 18 20 22 24 5V@3A 5V@6A
PRELIMINARY
3.3V Line Regulation
3.34 3.335 3.33 Vout (V) 3.3V@0A 3.325 3.32 3.315 3.31 10 12 14 16 Vin (V) 18 20 22 24 3.3V@3A 3.3V@6A
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SC1403
POWER MANAGEMENT Typical Characteristics (Cont.)
5V Load Regulation @Vin =19V
5.05 5.04 5.03 5.02 Vout (V) 5.01 5 4.99 4.98 4.97 4.96 0 1 2 3 Iout (A) 4 5 6 5V @ 25degC 5V @125degC 5V@-45degC
PRELIMINARY
5V Load Regulation @ Vin =10V
5.03 5.02 5.01 5 Vout (V) 5.0V@25degC 4.99 4.98 4.97 4.96 4.95 0 1 2 3 Iout (A)
2002 Semtech Corp. 23 www.semtech.com
5.0V@125degC 5.0V@-45degC
4
5
6
SC1403
POWER MANAGEMENT
3.3V Load Regulation @ Vin = 19V
3.35
PRELIMINARY
3.34
3.33 Vout (V) 3.3V@125degC 3.32 3.3V@-45degC 3.3V@25degC 3.31
3.3
3.29 0 1 2 3 Iout (A) 4 5 6
3.3V Load Regulation @ Vin =10V
3.34 3.335 3.33 3.325 3.32 Vout (V) 3.315 3.31 3.305 3.3 3.295 3.29 3.285 0 1 2 3 Iout (A) 4 5 6 3.3V@25degC 3.3V@125degC 3.3V@-45degC
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SC1403
POWER MANAGEMENT
5V Efficiency
97.00%
PRELIMINARY
95.00%
93.00% Efficiency (%) 5Vout@19Vin 5Vout@10Vin
91.00%
89.00%
87.00%
85.00% 0.01 0.1 Iout (A) 1 10
3.3V Efficiency
95.00%
90.00%
Efficiency (%)
85.00% 3.3Vout@19Vin 3.3Vout@10Vin 80.00%
75.00%
70.00% 0.01 0.1 Iout (A)
2002 Semtech Corp. 25 www.semtech.com
1
10
VIN J24
1 VIN_5V 1 C 4 2 1 R 1 2 2 JP2 10m 2 8.06k C_5 1 C_3 1 1 2 100pF 1 C14 8.06k R 4 R 5 2 10 R 3 2 BAT54A V+ VL 1 D 1 1 0.22uF
VIN
V+S
NEG
J1
2 1
POS
1
C1 C5 10uF/25V 1 10uF/25V
C OMP3 2
2 C OMP5
2
C2 C6
JP1 R 2 10m
C 3
2
1 VIN_3V 2
1
1
1
GND
GND
GND
1
8 7 6 5
5 6 7 8
POWER MANAGEMENT Evaluation Board Schematic
4
DH 3 1 C15 R 6 0 3 2 1 R 7 2 DL3 2 BST3R BST5R LX 5 DL5 0 0.22uF C16 BST5
B_JACK_PAIR 1 2 3
J19 L1 5.6uH
5 6 7 8 LX 3 0.22uF
+3.3V
IRF7413 IRF7413
POS
1
+3.3V
R8
1
NEG
2
D
8 7 6 5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
V+
VL
140T3
2 C23 2 C24 NO_POP 1 R11 NO_POP 1 0.1uF 2 FB5 C25 R12 2 2 1 JP6 NO_POP 1 NO_POP 2 1
DL3
ON3
DH 3
DH 5
BST3
BST5
SEQ
SH DN
PGND
140T3
DL5 SEQ 4 2 2 2 PHASE3
1
C21
Q3 140T3
3 2 1 1 2 3
CSH 3
CSL3
FB3
C OMP3
C OMP5
SYNC
ON5
GND
R EF
PSAVE
R ESET
FB5
CSL5
CSH 5
1
1
NO_POP 1 NO_POP 1 VL 1 2 3 4 5 6 7 8 9 10 11 12 13 14
2
1
2
JP7 T-ON5 R14 R15 R17 C30 ON3 C31 0.01uF 1 R18 VIN 2 C33 0.01uF 2 0 1 C32 6 7 8 9 10 0.01uF 1k 5 4 3 2 1 2 ON5_RC 1 1 R19 SW1 D IP_SW5_PTH VL SHDN# 1 2M 2 2M 2 2 2M 2 R16 2M 1 0.01uF SYNC 1 2M 2
R13 PSV#
2 C26
C OMP5
C OMP3
1
2
26
IRF7413
JP3 JP4 JP5
R10
2
U1
SC1403TS
C22
0.1uF
PHASE5
4
D5
150uF/6.3V NO_POP
IRF7413
CSH 5
CSH 3
FB3 RESET# R EF C27 0.01uF C28 1uF/16V C29 0.1uF
NEG
2002 Semtech Corp.
C9
4.7uF/35V 0.1uF C10
B_JACK_PAIR
10uF/25V 1
10uF/25V 1
0.22uF
J2
J3
J4
J5
GND
C11 Q1
C13 100pF 2
D
C12 0.1uF
Q2
D
4.7uF/16V
BST3 DH 5 4
+5V J18
D2 L2 Q4 5.6uH 5m R9 C19
C17
C18
5m
180uF/4V
NO_POP
B_JACK_PAIR +5V 1 POS
140T3 D3
C20
D4
NO_POP
1
NO_POP
REF J9
1
REF J11
1 1
SYNC
1
ON3
J10
1
T-ON5
J12
J13
PSV# RESET# RESET# VL VL
1
1
SHDN#
J14
1
J16
J15
Title Size
R31
1
SC1403 Demonstration Board
D ocument Number Rev
B
Date:
RTPA00024
Tuesday, April 02, 2002 Sheet 1 of 3
PRELIMINARY
SC1403
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1
SC1403
POWER MANAGEMENT Evaluation Board Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 Quanity 1 1 1 2 1 4 7 7 2 3 13 Designation C 25 C 17 C 19 C 28, C 29 D1 D2,D3,D4,D5 D 6, D 7, D 8, D 9, D10, D11, D12 JP 1 , JP 2 , JP 3 , JP 4 , JP 5 , JP 8 , JP 9 JP 6 , JP 7 , J1 , J6 , J7 J2 , J3 , J4 , J5 , J8 , J10, J11, J12, J13, J14, J15,2J9 L1, L2 Q1, Q2, Q3, Q4 Q5, Q6, Q7, R1 R4, R5 R6, R7 R14, R12, R15, R17 R28, R16 R21, R23, R25, R26 R18, R19 SW1 U1 U3 SSLI306T-5R6M-S IRF7413 MMBF170LT1 Any Any
WSL2512R0055FB43
PRELIMINARY
Description 1uF, 16V 180uF, 4V 150uF, 6.3V 1uF, 10V 30V, 200ma, dual C_Anode 40V, 1A Schottky Surface mount LED 2 Pin Berg Connector Manufacturer Panasonic Panasonic Panasonic Panasonic Zetex Motorola Kingbright Berg Device 1206
D _ C a se _ 7 3 4 3 D _ C a se _ 7 3 4 3
Part Number E C J3 F B 1 C 1 0 5 EEF-UE0G181R EEF-UE0J151R E C J2 F B 1 A 1 0 5 K BAT54A MBRS140T3 APTR3216
805 SOT-23 SMB 1206
3Pin Berg Connector Berg Banana Jack Pair Test Points
12 13 14 15 16 17 18 19 20 21 22 23 24
2 4 3 1 2 2 4 2 4 2 1 1 1
SMT Inductor 5.6uH 30V N-channel MOSFET 500mA, 60V N-channel FET 10ohm 0ohm 5.5mohm 2Megohm 1Kohm 2.37ohm 10Kohm 4-position Dip Switch Mobile PWM Controller with VCS Regulated Charge Pump with 120mA Output
Yageo/Act International Rectifier
On-Semiconductor
SO8 SOT23 603 603 2512 603 603 603 603
Any Any Vishay Dale Any Any Any Any C&K SEMTECH SEMTECH
Any Any Any Any B D 04 SC1403TS S C 1412
TSSOP28 MSOP10
2002 Semtech Corp.
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SC1403
POWER MANAGEMENT Evaluation Board Bill ofMaterials
Item 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Quantity Designator 4d 1d 5d 2d 4d 2d 3d 1d 1d 2d 2d 1d 1d 1d C1,C2,C5,C6 C11 C 10, C 12, C 26, C 33 C 7, C 8 C 3, C 4, C 15, C 16 C 13, C 14 C 30, C 31, C 32 C 27 C 25 R22, R24 R2, R3 R29 R27 R13 E C J1 V B 1 C 1 0 4 K E C J3 F B 1 C 1 0 5 Any Any Any Any Any ECJ-2YB1H104K ECJ-2YB1H101K ECJ-2VF1H224Z ECJ1VC1H47K Part Number GRM230Y5V106Z025 Description 10uF, 25V 4.7uF, 20V 0.1uF,50V, X7R 100pF, 50V, X7R 0.22uF,50V, Y5V 4700pF, 50V 10uF, 16V 0.01uF,50V 1uF, 16V 20Kohm 8.06Kohm 300ohm 130ohm 100Kohm Panasonic Panasonic Any Any Any Any Any Panasonic Panasonic Panasonic Panasonic Murata
PRELIMINARY
Manufacturing Device 1210 B _ ca se 805 603 805 603 1206 603 1206 603 603 603 603 603
Top Assembly
Bottom Assembly
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SC1403
POWER MANAGEMENT Layout Guidelines
As with any high frequency switching regulator design, a good PCB layout is very essential in order to achieve optimum noise, efficiency, and stability performance of the converter. Before starting to layout the PCB, a careful layout strategy is strongly recommended. See the PCB layout in the SC1403 Evaluation Kit manual for example. In most applications, we recommend to use FR4 with 4 or more layers and at least 2 oz copper (for output current up to 6A). Use at least one inner layer for ground connection. And it is always a good practice to tie signal ground and power ground at one single point so that the signal ground is not easily contaminated. Also be sure that high current paths have low inductance and resistance by making trace widths as wide as possible and lengths as short as possible. Properly decouple lines that pull large amounts of current in short periods of time. The following step by step layout strategy should be used in order to fully utilize the potential of SC1403. Step #1. Power train components placement. a. Power train arrangement. Place power train components first. The following figure shows the recommended power train arrangement. Q1 is the main switching FET, Q2 is the synchronous Rectifier FET, D1 is the Schottky diode and L1 is the output inductor. The phase node, where the source of
PRELIMINARY
Minimize the length of current sense signal trace. Keep it less than 15mm. Kevin connection should be used and try to keep the traces parallel to each other and have them close to each other as much as possible. Even though SC1403 implements Virtual Current Sense scheme, output signal is sampled by the SC1403 to determine the PSAVE threshold. See the following figure for Kelvin connection for current sense signal hook up.
L1
SC1403
CSH CSL Rcs
c. Gate Drive. SC1403 has built-in gate drivers capable of sinking/sourcing 1A pk-pk. Upper gate drive signals are noisier than the lower ones. Therefore, place them away from sensitive analog circuitries. Make sure the lower gate traces are as close as possible to the IC pins and both upper and lower gate traces as wide as possible. Step #2: PWM controller placement (pins) and signal ground island. Connect all analog grounds to a separate solid copper island plane, which connects to the SC1403's GND pin. This includes REF, FB3, FB5, COMP3, COMP5, SYNC, ON3, ON5, PSV# and RESET#. Step #3: Ground plane arrangement.
Q1 D1 Q2 L1
upper switching FET and the drain of the synchronous rectifier meets, since it switches at very high rate of speed, is generally the largest source of common-mode noise in the converter circuit. It should be kept to a minimum size consistent with its connectivity and current carrying requirements. Also place the Schottky diode as close to the phase node as possible to minimize the trace inductance, therefore reduce the efficiency loss due to the current ramp-up and down time. This becomes extremely important when converter needs to handle high di/dt requirement. b. Current Sense.
There are several ways to tie the different grounds together. Analog Ground, Power Ground for the input side and Power Ground for the output side. Since this is a buck topology converter, the output is relatively quieter than the input side. That is where we choose to tie the analog ground to the power ground through a 0 resistor. The power ground for the input side and the power ground for the output side is the same ground and they can be tied together using internal planes.
2002 Semtech Corp.
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SC1403
POWER MANAGEMENT Outline Drawing - TSSOP-28 PRELIMINARY
Land Pattern - TSSOP-28
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2002 Semtech Corp.
30
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